LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;

entity dec_chip is 
port(
		rst	   :in std_ulogic;
		clk_l 	   :in std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r      :in std_ulogic;
		m1_en	   :in std_ulogic;		 --mem1
		cmd1       :in std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1	   :in word16;			 --mem1	
		data1      :in word32;		 	 --mem1	
		ack1       :out std_ulogic;              --mem1
		m2_en	   :in std_ulogic;		 --mem2
		cmd2       :in std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2	   :in word16;			 --mem2	
		data2      :out word16;			 --mem2	
		ack2       :out std_ulogic;              --mem2
		wb_clk    :in std_ulogic;
		wb_en     :in std_ulogic;
		wb_addr   :in word16;
		wb_data   :in word16;
		irq        :out std_ulogic   ;            -- one frame ended (interruption);
		debug_en : in std_ulogic;
    debug_clk : out std_ulogic;
    debug_sel : in std_ulogic;
    debug_data: out std_ulogic_vector(31 downto 0); 	
		LKDT       :out std_ulogic;	
		N     : in std_ulogic_vector(3 downto 0);
		M     : in std_ulogic_vector(6 downto 0);
		OD    : in std_ulogic_vector(1 downto 0);
		BP    : in std_ulogic;		
		PDRST : in std_ulogic
		);
	end dec_chip;
	 architecture rtl of dec_chip is 
	  component  dec_io   
    port(
		rst	   :in std_ulogic;
		clk_l 	   :in std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r      :in std_ulogic;
		m1_en	   :in std_ulogic;		 --mem1
		cmd1       :in std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1	   :in word16;			 --mem1	
		data1      :in word32;		 	 --mem1	
		wb_clk    :in std_ulogic;
		wb_en     :in std_ulogic;
		wb_addr   :in word16;
		wb_data   :in word16;
		m2_en	   :in std_ulogic;		 --mem2
		cmd2       :in std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2	   :in word16;			 --mem2	
		debug_en : in std_ulogic;
                debug_sel : in std_ulogic;
		data2      :out word16;			 --mem2	
		ack2       :out std_ulogic;              --mem2
		ack1       :out std_ulogic;              --mem1
		irq        :out std_ulogic   ;            -- one frame ended (interruption);
                debug_clk : out std_ulogic;
                debug_data: out std_ulogic_vector(31 downto 0); 	
		LKDT       :out std_ulogic;
		N     : in std_ulogic_vector(3 downto 0);
		M     : in std_ulogic_vector(6 downto 0);
		OD    : in std_ulogic_vector(1 downto 0);
		BP    : in std_ulogic;		
		PDRST : in std_ulogic;

		rst_c	   :out std_ulogic;
		clk_l_c 	   :out std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r_c      :out std_ulogic;
		m1_en_c	   :out std_ulogic;		 --mem1
		cmd1_c       :out std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1_c	   :out word16;			 --mem1	
		data1_c      :out word32;		 	 --mem1	
		wb_clk_c    :out std_ulogic;
		wb_en_c     :out std_ulogic;
		wb_addr_c   :out word16;
		wb_data_c   :out word16;
		m2_en_c	   :out std_ulogic;		 --mem2
		cmd2_c       :out std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2_c	   :out word16;			 --mem2	
		debug_en_c : out std_ulogic;
                debug_sel_c : out std_ulogic;
		data2_c      :in word16;			 --mem2	
		ack2_c       :in std_ulogic;              --mem2
		ack1_c       :in std_ulogic;              --mem1
		irq_c        :in std_ulogic   ;            -- one frame ended (interruption);
                debug_clk_c : in std_ulogic;
                debug_data_c : in std_ulogic_vector(31 downto 0); 	
		LKDT_c       :in std_ulogic;
		N_c     : out std_ulogic_vector(3 downto 0);
		M_c     : out std_ulogic_vector(6 downto 0);
		OD_c    : out std_ulogic_vector(1 downto 0);
		BP_c    : out std_ulogic;		
		PDRST_c : out std_ulogic
		);
end component ;
component dec_top  port 
(
		rst	   :in std_ulogic;
		clk_l 	   :in std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r      :in std_ulogic;
		m1_en	   :in std_ulogic;		 --mem1
		cmd1       :in std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1	   :in word16;			 --mem1	
		data1      :in word32;		 	 --mem1	
		ack1       :out std_ulogic;              --mem1
		m2_en	   :in std_ulogic;		 --mem2
		cmd2       :in std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2	   :in word16;			 --mem2	
		data2      :out word16;			 --mem2	
		ack2       :out std_ulogic;              --mem2
		wb_clk    :in std_ulogic;
		wb_en     :in std_ulogic;
		wb_addr   :in word16;
		wb_data   :in word16;
		irq        :out std_ulogic   ;            -- one frame ended (interruption);
		debug_en : in std_ulogic;
    debug_clk : out std_ulogic;
    debug_sel : in std_ulogic;
    debug_data: out std_ulogic_vector(31 downto 0); 	
		LKDT       :out std_ulogic;	
		N     : in std_ulogic_vector(3 downto 0);
		M     : in std_ulogic_vector(6 downto 0);
		OD    : in std_ulogic_vector(1 downto 0);
		BP    : in std_ulogic;		
		PDRST : in std_ulogic
		);
	end component;
	 
	  signal  rst_c	   :std_ulogic;
	signal clk_l_c 	   : std_ulogic;               --clk_l low frequency, clk_h high frequency
	signal clk_r_c      : std_ulogic;
	signal m1_en_c	   : std_ulogic;		 --mem1
	signal 	cmd1_c       : std_ulogic;               --mem1 (wr='1' | rd='0')
	signal	addr1_c	   : word16;			 --mem1	
	signal	data1_c      : word32;		 	 --mem1	
	signal	wb_clk_c    : std_ulogic;
	signal	wb_en_c     : std_ulogic;
	signal	wb_addr_c   : word16;
  signal		wb_data_c   : word16;
	signal m2_en_c	   : std_ulogic;		 --mem2
	signal	cmd2_c       : std_ulogic;               --mem2 (wr='1' | rd='0')
	signal addr2_c	   : word16;			 --mem2	
	signal	debug_en_c :  std_ulogic;
 signal  debug_sel_c :  std_ulogic;
	signal data2_c      : word16;			 --mem2	
		signal ack2_c       : std_ulogic;              --mem2
		signal ack1_c       : std_ulogic;              --mem1
		signal irq_c        : std_ulogic   ;            -- one frame ended (interruption);
       signal         debug_clk_c :  std_ulogic;
            signal    debug_data_c :  std_ulogic_vector(31 downto 0); 	
signal		LKDT_c       : std_ulogic;
signal		N_c     :  std_ulogic_vector(3 downto 0);
	signal	M_c     :  std_ulogic_vector(6 downto 0);
	signal	OD_c    :  std_ulogic_vector(1 downto 0);
signal		BP_c    :  std_ulogic;		
	signal	PDRST_c :  std_ulogic;
	begin 
	  
	 dio : dec_io port map (
	  rst	  => rst, 
		clk_l 	  => clk_l,
		clk_r     => clk_r,
		m1_en	   => m1_en,
		cmd1      => cmd1,
		addr1	  => addr1,
		data1    => data1,
		ack1     => ack1,
		m2_en	=> m2_en,
		cmd2   => cmd2,   
		addr2	   => addr2,
		data2   => data2,
		ack2    => ack2,   
		wb_clk  => wb_clk,  
		wb_en   => wb_en,  
		wb_addr   => wb_addr,
		wb_data  => wb_data,
		irq      => irq, 
		debug_en => debug_en,
    debug_clk => debug_clk,
    debug_sel => debug_sel,
    debug_data	=> debug_data,
		LKDT     => LKDT,
		N     => N,
		M    => M,
		OD  => OD, 
		BP   => BP,
		PDRST => PDRST,
		rst_c	  =>rst_c,
		clk_l_c 	=> clk_l_c,   
		clk_r_c  => clk_r_c,   
		m1_en_c	  => m1_en_c,
		cmd1_c     => cmd1_c,  
		addr1_c	   => addr1_c,
		data1_c    =>data1_c,
		wb_clk_c  => wb_clk_c, 
		wb_en_c    => wb_en_c, 
		wb_addr_c  =>wb_addr_c,
		wb_data_c   => wb_data_c,
		m2_en_c	 =>m2_en_c, 
		cmd2_c     => cmd2_c, 
		addr2_c	  => addr2_c,
		debug_en_c => debug_en_c,
                debug_sel_c => debug_sel_c,
		data2_c    => data2_c, 
		ack2_c    => ack2_c, 
		ack1_c     => ack1_c, 
		irq_c     => irq_c, 
                debug_clk_c => debug_clk_c,
                debug_data_c  	=> debug_data_c,
		LKDT_c     => LKDT_c,
		N_c => N_c,    
		M_c   => M_c, 
		OD_c   => OD_c, 
		BP_c  => BP_c ,
		PDRST_c => PDRST_c );
		
		
		
		core  : dec_top port map
		(rst	  => rst_c,
		clk_l 	=> clk_l_c,   
		clk_r  => clk_r_c,   
		m1_en	  => m1_en_c,
		cmd1     => cmd1_c,  
		addr1	   => addr1_c,
		data1    =>data1_c,
		wb_clk  => wb_clk_c, 
		wb_en    => wb_en_c, 
		wb_addr  =>wb_addr_c,
		wb_data   => wb_data_c,
		m2_en	 =>m2_en_c, 
		cmd2     => cmd2_c, 
		addr2	  => addr2_c,
		debug_en => debug_en_c,
    debug_sel => debug_sel_c,
		data2    => data2_c, 
		ack2    => ack2_c, 
		ack1     => ack1_c, 
		irq    => irq_c, 
    debug_clk => debug_clk_c,
  debug_data  	=> debug_data_c,
		LKDT     => LKDT_c,
		N => N_c,    
		M   => M_c, 
		OD   => OD_c, 
		BP  => BP_c ,
		PDRST => PDRST_c 
		
		
		); 
	  
	  
	  
	  
	  
	  
	  
	  
	  
	  end rtl;
